FIG. 1 illustrates a current digital-to-analog converter (DAC) 100 that accepts a multi-bit digital input signal 102, and outputs an analog current 106 indicative of the digital input signal 102. In FIG. 1 the DAC 100 is shown as receiving 10 bits, labeled D[9:0], where bit position 0 is the least significant bit (LSB) and bit position 9 is the most significant bit (MSB). Thus, the DAC 100 can be referred to as a 10-bit DAC, or equivalently as a DAC having 10-bits of resolution. While DAC 100 is shown as having 10 bits of resolution, more or less bits can be used, depending upon the desired resolution of the DAC.
FIGS. 2A and 2B illustrate exemplary transfer functions for a DAC, also referred to as DAC transfer functions. More specifically, FIG. 2A illustrates a linear DAC transfer function 201, and FIG. 2B illustrates a non-linear DAC transfer function 211. The non-linearity of the transfer function shown in FIG. 2B can be due to component and/or current mismatches as well as other non-idealities within the DAC, as will be appreciated from the discussion below.
The current DAC 100 (which will simply be referred to hereafter as “the DAC”) can be implemented using multiple current sources, as is well known in the art. For example, the 10-bit DAC 100 can include (2^10)−1 (i.e., 1023) equally weighted current sources, which are selectively turned on and off based on the digital input D[9:0], such that 2^10 (i.e., 1024) different analog current levels can be produced at the output of the DAC. Alternatively, less current sources can be used where the current sources are appropriately differently weighted. For example, as few as 10 differently weighted current sources may be used, each of which is controlled by one of the 10 bits. Many variations of this are possible, as is well known in the art.
One type of DAC is known as a segmented DAC, because it essentially includes a plurality of sub-DACs that form the larger DAC. There are numerous ways to implement a segmented DAC, not all of which are described herein. Typically each sub-DAC will receive at least some of the bits of the digital data input (e.g., D[9:0]) and generate a current output in response to the digital input. The currents output by the plurality of sub-DACs are typically added to produce the output of the larger DAC. Each sub-DAC can receive a corresponding reference current Iref that is used by the sub-DAC to calibrate the internal current sources (within the sub-DAC) that are used to convert a digital input to an analog output. The various reference currents Iref can be automatically adjusted, e.g., using feedback and/or a master reference current, in an attempt to compensate for component and current mismatches between the sub-DACs, to attempt to cause the larger DAC to be substantially linear (e.g., so that transfer function of the larger DAC resembles line 201 in FIG. 2A).
The above described segmented DACs are useful where the desire is to provide a DAC having a substantially linear DAC transfer function. However, that may not always be the desire.